Apply To Indie
In this position, the IC Engineer is a technical staff member responsible for managing and executing all activities associated with design, integration, verification and maintenance of mixed signal ICs in the area of embedded microcontroller-based system solutions. The verification responsibilities will include establishing verification strategies in line with the company objectives, and building System Verilog-based constraint-driven test benches. The IC design responsibilities will include building digital components based on customer application specific requirements or IP standards and to support the team to complete the design including tasks such as top-level integration, physical design support (constraints and gate level verification).
Successful applications will need a master's degree in electrical engineering or equivalent, and 8 or more years of digital verification experience. In addition they must have expert understanding of code and functional coverage-driven verification closure and be able to set up and deploy verification strategies based on directed testing, randomization, assertions and architectural performance testing to achieve intended coverage. Additional areas of required expertise include:
- Demonstrated knowledge of designing digital blocks using Verilog code.
- In-depth knowledge of CPU architecture (preferably ARM), communications peripherals, multi-domain clocking, bus and interconnect structures and power management
- Demonstrated knowledge of digital circuit simulation tools and front end environments, particularly Cadence based.
- Demonstrated knowledge of lab equipment tools such a logic analyzer, in particular demonstrate proficiency working with USB standard based products
- Demonstrated Knowledge of silicon process technologies and its associated library kits
- Demonstrated knowledge of revision control systems
- Programming in skill, perl, python languages. Excellent communication and leadership skills would also be a plus in this role.
The work location for this role will be indie's offices in Aliso Viejo, CA.
Send resume to: email@example.com
Successful applicants will be required to:
Indie is seeking talented chip designers to design and manage analog & RF custom ICs, with a particular interest in power management experience. Applications cover a broad range covering markets including health, automotive, industrial and IoT business opportunities. Successful applicants will be required to:
• Ownership of the entire Physical Design (PD) flow at block and chip level.
• Technology ranging from 0.35um to 28nm Mixed Signal including RF design and advanced power management flow (UPF/CPF).
• Lead the entire flow from synthesis flow setup to physical and power verification, including DRC and LVS.
• Leadership in flow generation, work closely with digital, DFT and analog design teams.
• Report to chip lead on a project basis and senior management for daily work allocation.
• 5+ years of experience in physical design
• MS degree in Electrical and/or Computer Engineering
• Working knowledge of Cadence place & route tools and Static Timing Analyzers
• Good understanding of timing requirements, clock tree generation and DFT insertion techniques.
• Physical verification (DRC/LVS) is a plus
• Support Post layout simulations and Timing Analysis
• Power / IR drop analysis - advantage
• Great communication skills
The design team at Indie Semiconductor develops various application specific customer centric designs. This physical design function will cover design topics such as pure digital advanced microcontrollers as well as complex mixed signal systems that includes power management, high speed design, sensor front end and GHz radios. Indie Semiconductor is looking at hiring a dedicated team member for Full Chip and Block Level Place and Route and the responsibility in this role involves optimizing and resolving multi mode timing constraints, capabilities to develop a strategy to draw power mesh with optimum floorplan. The PD engineer will also run power optimization, IR drop analysis, multi-corner (MMMC) clock tree synthesis along with signal integrity, cross talk analysis as required by the project and technology of choice. Obviously, ECO management are also needed along with capabilities to develop generic reusable scripts to optimize specific design tasks. Having formal equivalence check knowledge would be a plus.
Job opportunity open to our Aliso Viejo CA and Austin TX offices.