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Job Overview:

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Do you enjoy working in a creative fast-growing entrepreneurial environment? With indie you´ll never walk alone! We place high value on our teams and pursue excellence for our employees and customers!

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Indie Semiconductor is a fabless semiconductor company specializing in the design of innovative mixed-signal System-on-Chip (SoC) solutions for automotive applications.

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Our design team develops custom and standard SoC solutions for automotive applications which integrate advanced digital ICs (Arm®Cortex® MCUs and/or DSP) with mixed-signal devices into a single System-in-Package (SiP). The mixed signal can include power management, RF, high voltage as well as high speed convertors allowing us to provide complete solutions to our international customer base.

 

VisionQ, a business unit of indie Semiconductor, is responsible for creating power-efficient System-on-Chip (SoC) ASIC devices for the automotive market.

 

You will be responsible for managing and executing all activities associated with design, integration, verification and maintenance of digital IPs integrated in IC used in the area of embedded microcontroller-based system solutions.

Key Responsibilities:

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• Block and chip-level verification using the industry standard UVM methodology

• Verification plan and methodology

• Test bench infrastructure development

• Creation of random and constrained random test cases

• Specification and collection of functional & code coverage

• Gate-level simulation with post-synthesis, and post-layout netlists with SDF annotation

• Interaction with the post-silicon validation team for ASIC bring-up and characterization

Main Requirements:

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With us, you must love being part of an organization where everyone makes a difference and contributes to the company's success. Creativity, Ownership and Excellence are what we value.

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These are the skills and know how an ideal candidate would bring. We understand that nobody is perfect! After all, your new job should challenge you and you should have the possibilities to grow.

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• Bachelor’s degree in Electrical/Computer Engineering

• 7+ years of complete life cycle experience with multiple ASICs

• Solid understanding of random and constrained random testing using UVM

• Excellent written and verbal communication skills as well as a proactive approach to problem solving

• Demonstrated, progressive hands-on experience with industry standard verification tools, specifications, protocols and VIP

• Prior hands-on experience with power intent verification (UPF), design prototyping on FPGA platforms, and emulation systems such as HAPS & Zebu desirable

 

Location:

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Aliso Viejo, California, USA