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Package Development Engineer (Taiwan or Aliso Viejo, USA)

Job Overview:

Do you enjoy working in a creative fast-growing entrepreneurial environment? With indie you´ll never walk alone! We place high value on our teams and pursue excellence for our employees and customers!

Indie Semiconductor is a fabless semiconductor company specializing in the design of innovative mixed-signal System-on-Chip (SoC) solutions for automotive applications.

Our design team develops custom and standard SoC solutions for automotive applications which integrate advanced digital ICs (Arm®Cortex® MCUs and/or DSP) with mixed-signal devices into a single System-in-Package (SiP). The mixed signal can include power management, RF, high voltage as well as high speed convertors allowing us to provide complete solutions to our international customer base. You will join a small team of highly competent engineers that are creating brand new designs to implement the advanced sensing, connectivity and control required to enable modern automotive applications.

Job Responsibilities:

  • Responsible for design of packages for new and existing IC designs for power and high-speed RF and digital applications.

  • Ensure that new and existing package designs meet power, thermal, mechanical, signal integrity, manufacturability, reliability, and testability requirements.

  • Seek out and evaluate technology offerings from packaging component and assembly vendors world-wide to ensure optimal technical and cost characteristics.

  • Collaborate with Design, Product, Foundry, and ATE/DVT Test teams to gather packaging requirements and guide the teams on silicon and test hardware design.

  • Recommend and guide ASIC designers and Layout engineers on the signal and power routing, silicon metallization scheme, and design and arrangement of bond-pad and bumps on the silicon.

  • Specify package qualification plan tailored for the package design and the intended application.

  • Evaluate and mitigate impact of Process Change Notifications (PCN) originating from packaging suppliers.

  • Review instances of package manufacturing excursions and disruptions and provide technical advice to product and quality engineering teams in assessing and dispositioning affected materials, root causing the problems, and in generating corrective actions for the suppliers.

  • Provide technical advice in creating a PFMEA relating the package assembly operation.

  • Update and maintain packaging related documentations and procedures.

  • Advice on resolving reliability-related device failures from the field or product qualifications.


With us, you must love being part of an organization where everyone makes a difference and contributes to the company's success. CreativityOwnership and Excellence are what we value.

These are the skills and know how an ideal candidate would bring. We understand that nobody is perfect! After all, your new job should challenge you and you should have the possibilities to grow.

  • Bachelors / Masters in a relevant field

  • 5+ years of experience on design of high power and high speed RF and digital flip-chip and wirebond packages.

  • 3+ years of experience on design of multi-chip and multi-layer substrate packages: aQFN, WLCSP, WLBGA, FCBGA, MISBGA, Embedded die package, and LGA.

  • Working knowledge of flip-chip package substrate design, wire-bond lead frame design, RDL and bump design, copper pillars, and signal and power integrity.

  • Working knowledge of package failure mode mechanisms and reliability model.

  • Familiarity with mechanical and thermal package simulations.

  • Familiarity with backend silicon layout tools.

  • Familiarity with package, substrate, and lead-frame assembly equipment and process integration.

  • Experience interfacing and negotiating with suppliers.

  • Fact-based, decision making skills with focus on root cause analysis.

Work Location: Taiwan or Aliso Viejo (California), USA

HR Contact:

Human Resource Department

Telephone: 949-608-0854

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