Do you enjoy working in a creative fast-growing entrepreneurial environment? With indie you´ll never walk alone! We place high value on our teams and pursue excellence for our employees and customers!
indie is an Autotech solutions innovator. We focus on edge sensors spanning multiple modalities including LiDAR, radar, ultrasound and vision for Advanced Driver Assistance Systems (ADAS), autonomous vehicles, connected car, user experience and electrification applications.
Reporting to the Digital Verification Manager, the candidate will execute and drive all aspects of pre-silicon verification with a goal of ensuring the highest quality first silicon. This is an experienced-level position.
Develop verification and coverage plan based on the design micro-architecture document
Architect verification environments for digital IPs, sub-system and chip-level
Execute verification plan, including design bring-up, DV environment bring-up, regression enabling for all assigned features
Work closely with design team to report and resolve bugs prior to tape-out
Drive verification methodology discussions, mentor and lead a team of verification engineers
With us, you must love being part of an organization where everyone makes a difference and contributes to the company's success. Creativity, Ownership and Excellence are what we value.
These are the skills and know how an ideal candidate would bring. We understand that nobody is perfect! After all, your new job should challenge you and you should have the possibilities to grow.
B.S. in Electrical Engineering or Computer Science; Master’s degree is preferred
10+ years of experience in digital design verification role preferably in a team setting
Track record as a contributor who has executed multiple successful tape-out cycles
Expert in object-oriented programming and constrained random verification concepts
Deep understanding of digital design concepts and System Verilog HDL
Advanced level user of verification methodologies such as UVM or eRM (Specman e)
Experience developing verification environments and re-usable components from scratch
Proficient in implementing checkers using System Verilog Assertions
Experience in using Cadence Incisiv or Mentor Questa tool suite for verification
Ability to quickly debug gate level simulations
Knowledge of communication protocols such as USB is a plus
Understanding of micro-processor bus fabric protocols such as AHB, APB, AXI is preferred
Experience working with revision control systems such as subversion, CVS
Experience writing scripts in languages such as Perl, Ruby, Python, or TCL
Familiarity with bug tracking tools such as JIRA
Team player with excellent oral and written communication skills
Human Resource Department