Do you enjoy working in a creative fast-growing entrepreneurial environment? With indie you´ll never walk alone! We place high value on our teams and pursue excellence for our employees and customers!
indie is an Autotech solutions innovator. We focus on edge sensors spanning multiple modalities including LiDAR, radar, ultrasound and vision for Advanced Driver Assistance Systems (ADAS), autonomous vehicles, connected car, user experience and electrification applications.
The Vision business unit of indie Semiconductor, is responsible for creating power-efficient System-on-a-Chip (SoC) ASIC devices for the automotive market targeting interior and exterior sensing systems.
This position entails ownership of the architectural requirements of all SoCs in the Vision BU’s roadmap. The ideal candidate will have extensive complete-lifecycle experience with SoC devices at multiple advanced technology nodes, and in multiple vertical market segments.
Translation of (often incompletely specified) customer/product requirements into actionable design specifications
Definition and documentation of ASIC architecture and close interaction with the design and verification teams
ASIC data plane architecture design to meet/exceed performance targets
Identification of design bottlenecks and power hotspots
Architectural trade-off analysis for meeting silicon PPA requirements
IP evaluation and qualification
Liaison with internal and external customers
With us, you must love being part of an organization where everyone makes a difference and contributes to the company's success. Creativity, Ownership and Excellence are what we value.
These are the skills and know how an ideal candidate would bring. We understand that nobody is perfect! After all, your new job should challenge you and you should have the possibilities to grow.
Bachelor’s degree in Electrical/Computer Engineering (Master’s degree desirable)
15+ years of hands-on experience in SoC architecture and implementation
Expert-level understanding of industry standards and bus/interface protocols
Knowledge of “Network on Chip” technologies for ASIC data planes
Experience with low-power design techniques
Familiarity with ARM processors and ecosystem
knowledge of image processing pipelines and neural compute engines
Familiarity with C/C++/System C/Python/System Verilog
Knowledge of functional safety and reliability
Outstanding communication skills
Human Resource Department