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indie Semiconductor is a fabless semiconductor company specializing in the design of innovative mixed-signal System-on-Chip (SoC) solutions for automotive applications.
Our design team develops custom and standard SoC solutions for automotive applications which integrate advanced digital ICs (Arm®Cortex® MCUs and/or DSP) with mixed-signal devices into a single System-in-Package (SiP). The mixed signal can include power management, RF, high voltage as well as high speed convertors allowing us to provide complete solutions to our international customer base.
The digital design team at indie Semiconductor seeks a DFT engineer who will execute all aspects of pre-silicon DFT insertion and verification and interface with test engineering team for ATE test program development and silicon bring up. You will report to the Digital Physical Design and DFT Manager.
Definition of DFT requirements and architecture based on project specification and IP’s content.
Implement and verify standard DFT techniques such as Scan and MBIST.
Work with Analog and Mixed signal designers to define and implement custom test logic for time effective IP testing.
Analyze chip and block test coverage and generate test patterns for ATE.
Generate test patterns for ATE including custom patterns for IP’s and functional test to improve test coverage or screen test escapes.
Support post-silicon ATE test program bring up and test time reduction.
With us, you must love being part of an organization where everyone makes a difference and contributes to the company's success. Creativity, Ownership and Excellence are what we value.
These are the skills and know how an ideal candidate would bring. We understand that nobody is perfect! After all, your new job should challenge you and you should have the possibilities to grow.
Bachelors / Masters in a relevant field.
5+ years industry experience in the implementation and verification of DFT/DFD techniques for mixed signal designs. A strong fundamental knowledge of DFT is required.
Understanding of core-based test methodology and scan isolation.
Knowledge of various fault models such as Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and Cell Aware.
Knowledge in JTAG, Scan Compression, ATPG, Fault Simulation, at-speed testing and MBIST.
Knowledge in test methodologies for mixed signal IP’s like ADC, DAC, Serdes.
Familiarity with System Verilog, UVM, and use of assertions during verification, is preferred.
MS degree in Electrical and/or Computer Engineering.
Great communication skills.
Human Resource Department