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Job Code | #549

Digital IC Design Verification Senior Staff Engineer


Rabat, Morocco

Job Overview:

Do you enjoy working in a creative fast-growing entrepreneurial environment? With indie you´ll never walk alone! We place high value on our teams and pursue excellence for our employees and customers!

indie Semiconductor is a fabless semiconductor company specializing in the design of innovative mixed-signal System-on-Chip (SoC) solutions for automotive applications.

The design team at indie Semiconductor develops various application specific customer centric designs using ARM Cortex-M based microcontrollers and integrate Analog, RF, Power Management bringing a complete solution to our diverse customer’s base across health, automotive, industrial and IoT business opportunities.  The digital design team at indie Semiconductor seeks a digital verification engineer who will execute all aspects of pre-silicon verification to ensure a bug-free first silicon. This position with report to the Digital Verification Manager.

Job Responsibilities:

  • Develop verification and coverage plan based on the design micro-architecture document

  • Architect verification environments for digital IPs, sub-system and chip-level

  • Execute verification plan, including design bring-up, DV environment bring-up, regression enabling for all assigned features

  • Debug test failures, track functional and code coverage metrics

  • Work closely with design team to report and resolve bugs prior to tape-out

  • Provide feedback on existing verification methodology and drive improvements

Job Requirements

With us, you must love being part of an organization where everyone makes a difference and contributes to the company's success. Creativity, Ownership and Excellence are what we value.

These are the skills and know how an ideal candidate would bring. We understand that nobody is perfect! After all, your new job should challenge you and you should have the possibilities to grow.

  • B.S. in Electrical Engineering +7 or more years of relevant experience or

  • Master’s degree +5 or more years of relevant experience

  • Knowledge in object-oriented programming and constrained random verification concepts

  • Good understanding of digital design concepts and System Verilog HDL

  • Working knowledge of verification methodologies such as UVM or eRM (Specman e)

  • Experience in using Cadence Incisiv or Mentor Questa tool suite for verification

  • Ability to quickly debug gate level simulations

  • Knowledge of communication protocols such as USB is a plus

  • Understanding of micro-processor bus fabric protocols such as AMBA - AHB, APB, AXI is preferred

  • Experience working with revision control systems such as subversion, CVS

  • Experience writing scripts in languages such as Perl, Ruby, Python, or TCL

  • Familiarity with bug tracking tools such as JIRA

  • Team player with excellent oral and written communication skills


Human Resource Department

Telephone: 949-608-0854

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