Reporting to the Digital Verification Manager, the candidate will execute and drive all aspects of pre-silicon functional safety verification with a goal of ensuring that the design is meeting the required hardware metrics and diagnostics coverage. This is an experienced-level position.

Job Responsibilities:

• Contribute to safety analysis processes (e.g. FMEAs, FTAs, FMEDAs, etc.)

• Analyze functional safety requirements.

• Develop FuSa verification plan based on the design safety architecture

• Architect verification environments for manual fault injection

• Validate safety mechanisms as defined by the safety architecture

• Execute FuSa verification plan by running fault campaigns on all the failure modes and for each block

• Work closely with design and fusa teams to report and resolve hardware metrics and/or diagnostics coverage

• Supports internal meetings.

• Supports customer review meetings.

• Supports Safety Assessment Reviews held by safety assessor.

• Drive fusa verification methodology discussions, mentor and lead a team of fusa verification engineers

Job Requirements

With us, you must love being part of an organization where everyone makes a difference and contributes to the company's success. Creativity, Ownership and Excellence are what we value.

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These are the skills and know how an ideal candidate would bring. We understand that nobody is perfect! After all, your new job should challenge you and you should have the possibilities to grow.

• B.S. in Electrical Engineering or Computer Science; Master’s degree is preferred

• 10+ years of experience in digital design verification role preferably in a team setting

• Track record as a contributor who has executed multiple successful tape-out cycles

• Deep understanding of digital design concepts and System Verilog HDL

• Expert in requirements managements and fusa cycle

• Deep understanding of manual and automated fault injection

• Advanced level user of safety analysis processes (e.g. FMEAs, FTAs, FMEDAs, etc.)

• Proficient in implementing usf constraints

• Experience in using Cadence Xcelium safety, vManager safety, midas, medini or equivalent tool suite for fusa verification

• Ability to quickly debug gate level simulations

• Experience writing scripts in languages such as Perl, Ruby, Python, or TCL

• Familiarity with bug tracking tools such as JIRA

• Familiarity with requirement management tools such as JAMA

• Team player with excellent oral and written communication skills